The present invention relates to a clock synchronization circuit and a semiconductor device having the clock synchronization circuit. More specifically, the present invention relates to a clock synchronization circuit for capturing data input thereto in synchronization with a clock signal and outputting the data, and a semiconductor device having the clock synchronization circuit.
In general, a digital signal processing device formed on a semiconductor chip includes a conventional clock synchronization circuit for synchronizing input data with a clock signal, and for transmitting the data to a processing circuit at a next stage. The conventional clock synchronization circuit may include a D flip-flop for capturing the data at a timing in synchronization with the clock signal and a clock buffer for supplying the clock signal supplied from an outside of the semiconductor chip to the D flip-flop (refer to Patent Reference).
Patent Reference: Japanese Patent Publication No. 11-15783
In the recent years, a finer semiconductor device process has become available. Further, a processing speed has increased, and a circuit size has become larger. With these trends, the number of the D flip-flops to be mounted on the semiconductor chip has increased. Accordingly, in the conventional clock synchronization circuit, power consumption has increased. Further, when the clock buffer and the D flip-flop are operated simultaneously, electromagnetic interference (EMI) tends to be generated more frequently due to an increase in a peak electric current.
In view of the problems described above, an object of the present invention is to provide a clock synchronization circuit and a semiconductor device capable of solving the problems of the conventional clock synchronization circuit. In the clock synchronization circuit and the semiconductor device of the present invention, it is possible to reduce power consumption and EMI.
Further objects and advantages of the invention will be apparent from the following description of the invention.